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ELEC 418 - Advanced Digital Systems - Spring 2008 |
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Section 01 |
TR 8:00-9:15 AM |
Room: GRIMS
328 |
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Section 81 |
MW 5:15-6:30 PM |
Room: GRIMS
328 |
Instructor: Dr. Ron Hayne,
Grimsley Hall Room 309, 843-953-2281, ron.hayne@citadel.edu
Office Hours: Mon/Wed 1:30-3:30 PM
Tue/Thur 2:30-3:30 PM
Wed 9:30-11:00 AM
Additional hours available by appointment
Required
Material: Digital Systems Design Using VHDL, Second Edition, Roth
Course Software: ModelSim PE Student Edition
GOALS: To familiarize students with the basic principles of digital systems design and the use of a hardware description language, VHDL, in the design process..
COURSE
OUTCOMES: At the end of the course
the student should:
· Be familiar with VHDL and modern digital design flow
· Be able to explain design examples including computer arithmetic and a RISC microprocessor
· Be able to explain the implementation and testing of digital systems using FPGAs
· Be able to write, compile, and simulate VHDL models of digital systems
CATALOG DESCRIPTION:
Prerequisite: ELEC 311, ELEC 330
Experience in advanced digital
design techniques and exposure to the development tools used in the design of
advanced digital systems. Topics include
the design of digital systems using VHDL, industry standard FPGA devices and
software, and microprocessor hardware components. Lecture:
three hours
ATTENDANCE
AND PARTICIPATION: Attendance is required. Should it be necessary to miss a class for
any reason the student will notify the professor in advance and will be
responsible for any material missed. Assigned
tests are mandatory. Unless authorized
to the contrary by the professor, such tests take precedence over all other
duties or activities. Absence in
excess of 20% of the class meetings may result in a failing grade for the
course.
ACADEMIC
INTEGRITY: Cheating in any form will be fully
prosecuted.
HOMEWORK: Homework will
be turned in at the beginning of class on the due date. Late homework will not be accepted and will
be given a zero grade. Neatness
(legibility) will count!
GRADING: (tentative)
(a) Homework and
Quizzes 30%
(b) Tests (2) 40%
(c) Final Exam
30%
SPECIAL ACCOMMODATIONS: If you need accommodations because of a disability, please see me privately after class or in my office within two weeks of the beginning of class or immediately after diagnosis. To request academic accommodations, students must also register with Academic Support at 953-1820.
COURSE OUTLINE: Changes are
not only possible, but likely.
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Dates |
Topics |
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1 |
1/7 - 1/10 |
Course Overview, Intro to VHDL |
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2 |
1/14 - 1/17 |
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3 |
1/22 - 1/24 |
Programmable Logic, Design Examples |
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4 |
1/28 - 1/31 |
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5 |
2/4 - 2/7 |
Designing with FPGAs |
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6 |
2/11 - 2/14 |
Review, Test 1 |
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7 |
2/18 - 2/21 |
SM Charts & Microprogramming |
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8 |
2/25 - 2/28 |
Floating-Point Arithmetic |
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9 |
3/3 - 3/6 |
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10 |
3/10 - 3/13 |
Additional VHDL |
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11 |
3/17 - 3/20 |
Review, Test 2 |
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12 |
3/24 - 3/27 |
Spring Furlough |
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13 |
3/31 - 4/3 |
RISC Microprocessor |
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14 |
4/7 - 4/10 |
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15 |
4/14 - 4/17 |
UART |
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16 |
4/21 - 4/22 |
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SCCC starts and finishes one class period
behind CGC
HOMEWORK AND PROJECTS
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Date Assigned |
Date Due |
Assignment |
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