ELEC 311 – Digital Logic and Circuits – Fall 2008

               Section 01                   TR 8:00-9:15 AM               Room: GRIMSLEY 305

               Section 02                  TR 9:30-10:45 AM              Room: GRIMSLEY 305

               Section 81                   TR 6:45-8:00 PM               Room: GRIMSLEY 305

             

Instructor:  Dr. Ron Hayne, Grimsley Hall Room 309, 843-953-2281, ron.hayne@citadel.edu

Office Hours:  MW 1:30-3:30 PM                             
TR 4:30-5:30 PM
W  9:00-10:30 AM

                        Additional hours available by appointment

Required Material:      Digital Design Principles and Practices, Fourth Edition, Wakerly, ISBN 0-13-186389-4
Course Software:        Xilinx ISE 9.1
                                    Adept Suite (ExPort)
                                    ModelSim XE

GOALS:  Introduce Boolean algebra, digital data coding, digital arithmetic and the basic techniques used to design, construct, and analyze combinational and sequential digital circuits.

COURSE OUTCOMES:  At the end of the course the student should:

·         Be able to design a digital system from a set of specifications or a description of the system

·         Be able to analyze and troubleshoot a digital system

·         Be able to write project summaries and communicate technical information

·         Be familiar with industry standard integrated circuits and design tools

ATTENDANCE AND PARTICIPATION:  Attendance is required.  Should it be necessary to miss a class for any reason the student will notify the professor in advance and will be responsible for any material missed.  Assigned tests are mandatory.  Unless authorized to the contrary by the professor, such tests take precedence over all other duties or activities.  Absence in excess of 20% of the class meetings may result in a failing grade for the course.

ACADEMIC INTEGRITY AND COLLABORATION:  Cheating in any form will be fully prosecuted.  Collaboration is allowed on homework assignments, but the submission must be the student's own work.  Projects will be done in groups of 2 and collaboration must be limited to within the group.  All exams and quizzes will be individual work.

HOMEWORK:  Homework will be turned in at the beginning of class on the due date.  Late homework will not be accepted and will be given a zero grade.  Neatness (legibility) will count!

GRADING: (tentative)

                        (a) Projects, Homework, and Quizzes 40%

                        (b) Tests (2) 30%

                        (c) Final Exam 30%

SPECIAL ACCOMMODATIONS   If you need accommodations because of a disability, please see me privately after class or in my office within two weeks of the beginning of class or immediately after diagnosis.  To request academic accommodations, students must also register with Academic Support at 953-1820.

Final Exams 

Section 01 – Dec 13, 8:00 AM; Section 02 – Dec 11, 1:00 PM; Section 81 – TBD

 

Course Outline

CGC

Date

SCCC

Date

Lesson

Topic

Reading

8/26

8/28

1

Introduction

Ch 1

8/28

9/2

2

Number Systems

2.1 - 2.8

9/2

9/4

3

Combinational Circuit Analysis

3.1, 4.1 - 4.2

9/4

9/9

4

Combinational Circuit Analysis

Project 1

9/9

9/11

5

Codes

2.10 - 2.16

9/11

9/16

6

Combinational Circuit Synthesis

4.3

9/16

9/18

7

Digital Circuits

3.2 - 3.7

9/18

9/23

8

Combinational Circuit Design

Project 2

9/23

9/25

9

VHDL

5.1, 5.3 - 5.3.6

9/25

9/30

 

Review

Ch 1 - Ch 4

9/30

10/2

 

Test #1

Ch 1 - Ch 4

10/2

10/7

10

VHDL

5.3.5 - 5.3.6

10/7

10/9

11

Decoders, Encoders, Multiplexers

6.4 - 6.7

10/9

10/14

12

Parity, Comparators, ALUs

6.8 - 6.11

10/14

10/16

13

Adder-Subtractor

Project 3

10/16

10/21

14

Sequential Analysis

7.1 - 7.3

10/21

10/23

15

Sequential Analysis & Design

 

10/23

10/28

16

Sequential Design

7.4 - 7.5

10/28

10/30

17

VHDL

5.3.7 - 5.3.12, 7.12

10/30

11/6

18

Sequential Design

Project 4

11/4

11/4

 

Design Practices (No Class)

6.1 - 6.3, 8.1 - 8.3

11/6

11/11

 

Review

Ch 5 - Ch 7

11/11

11/13

 

Test #2

Ch 5 - Ch 7

11/13

11/18

19

Counters, Shift Registers

8.4 - 8.5

11/18

11/20

20

Memory

9.1 - 9.4

11/20

12/2

21

CPLDs, FPGAs

9.5 - 9.6, Xilinx1, Xilinx2

11/27

11/27

 

Thanksgiving

 

12/2

12/4

 

Review

Ch 1 - Ch 9

12/4

12/9

 

Review          

Ch 1 - Ch 9

 

HOMEWORK AND PROJECTS

Date Assigned

Date Due

Assignment

Aug 28, Sep 2

Sep 11, 16

Homework 1

Sep 4, 9

Sep 18, 23

Project 1

Sep 16, 18

Sep 25, 30

Homework 2

Sep 18, 23

Oct 7, 9

Project 2

Oct 7, 9

Oct 16, 21

Homework 3

Oct 14, 16

Oct 28, 30

Project 3, project3_gates.vhd

Oct 23, 28

Nov 6, 11

Homework 4

Oct 30, Nov 6

Nov 18, 20

Project 4, project4_pkg.vhd

Nov 18, 20

Dec 4, 9

Homework 5